Cost-Effective Hardware-Sharing Design of Fast Algorithm Based Multiple Forward and Inverse Transforms for H.264/AVC, MPEG-1/2/4, AVS, and VC-1 Video Encoding and Decoding Applications.

In this letter, multiple forward and inverse fast algorithm based transforms and their hardware-sharing design for 2<inline-formula> <tex-math notation="TeX">$\,\times\,$ </tex-math></inline-formula>2, 4<inline-formula> \,\times\,$ </tex-math></inline-formula>4, and 8<inline-formula> \,\times\,$ </tex-math></inline-formula>8 transforms in H.264/AVC, and the 8<inline-formula> \,\times\,$ </tex-math></inline-formula>8 transform in audio video coding standard, 4<inline-formula> \,\times\,$ </tex-math></inline-formula>4 and 8<inline-formula> -math notation="TeX" </tex-math></inline-formula> CMOS technology, the proposed 2-D transform architecture has less normalized power per mode and larger normalized hardware efficiency than the previous multiple-standard designs. The cost-effective 2-D full pipelined transform achieves multistandard real-time 1080HD at 60-Hz video encoding and decoding applications. [ABSTRACT FROM PUBLISHER]