FPGA IMPLEMENTATION OF HIGH SPEED AND LOW POWER ARCHITECTURES FOR IMAGE SEGMENTATION USING SOBEL OPERATORS.

In this paper we present two architectures for image segmentation using Sobel Operators. The first architecture is designed for optimum speed whereas the second one is designed for low power. To improve the speed of operation and to reduce the memory access two identical processing units operate parallelly. The first architecture is able to segment up to 800 images each of 640 x 480 pixels in one second at 500 MHz clock frequency consuming 27.31 mW dynamic power. The second architecture is able to segment up to 488 images each of 640 x 480 pixels in one second at 300 MHz clock frequency consuming 13.6mW dynamic power. [ABSTRACT FROM AUTHOR]