Back to Search
Start Over
On Automatic-Verification Pattern Generation for SoC With Port-Order Fault Model.
- Source :
-
IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems . Apr2002, Vol. 21 Issue 4, p466. 14p. 3 Black and White Photographs, 18 Diagrams, 2 Charts. - Publication Year :
- 2002
-
Abstract
- Presents an automatic-verification pattern generation (AVPG) for system-on-a-chip design verification based on the port-order fault (POF) model. Details of experiments on combinational and sequential benchmarks; Mechanism of conducting POF verification; Description of a verification pattern generation algorithm; Discussion on the combinational AVPG.
- Subjects :
- *COMPUTER circuits
*ALGORITHMS
Subjects
Details
- Language :
- English
- ISSN :
- 02780070
- Volume :
- 21
- Issue :
- 4
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems
- Publication Type :
- Academic Journal
- Accession number :
- 6459311
- Full Text :
- https://doi.org/10.1109/43.992770