Cite
Current-density centric logical effort delay model for high-speed current-mode logic circuits.
MLA
Hu, Y., and R. Bashirullah. “Current-Density Centric Logical Effort Delay Model for High-Speed Current-Mode Logic Circuits.” Electronics Letters (Institution of Engineering & Technology), vol. 47, no. 16, Aug. 2011, pp. 906–07. EBSCOhost, https://doi.org/10.1049/el.2011.0673.
APA
Hu, Y., & Bashirullah, R. (2011). Current-density centric logical effort delay model for high-speed current-mode logic circuits. Electronics Letters (Institution of Engineering & Technology), 47(16), 906–907. https://doi.org/10.1049/el.2011.0673
Chicago
Hu, Y., and R. Bashirullah. 2011. “Current-Density Centric Logical Effort Delay Model for High-Speed Current-Mode Logic Circuits.” Electronics Letters (Institution of Engineering & Technology) 47 (16): 906–7. doi:10.1049/el.2011.0673.