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Low-power VCO with phase-noise improvement in 0.18 µm CMOS technology.

Authors :
Liang, C.-P.
Huang, T.-J.
Rao, P.-Z.
Chung, S.-J.
Source :
Electronics Letters (Institution of Engineering & Technology). 9/30/2010, Vol. 46 Issue 20, p1385-1387. 3p. 1 Diagram, 1 Chart, 3 Graphs.
Publication Year :
2010

Abstract

A low-power 5.25 GHz voltage-controlled oscillator (VCO) with phase-noise improvement is designed in a 0.18 µm CMOS 1P6M process. Owing to the use of a larger value of parallel capacitor, an additional harmonic-suppressed capacitor, and an appropriate bulk bias voltage of transistor, a good figure of merit of -190 dBc/Hz can be achieved without extra chip area and CMOS process steps. The fabricated VCO operates from 5.12 to 5.36 GHz with a core power consumption of 1.9 mW and active chip area of 0.15 mm2. The measured phase noise at 1 MHz offset is about -119 dBc/Hz. [ABSTRACT FROM AUTHOR]

Details

Language :
English
ISSN :
00135194
Volume :
46
Issue :
20
Database :
Academic Search Index
Journal :
Electronics Letters (Institution of Engineering & Technology)
Publication Type :
Academic Journal
Accession number :
53980550
Full Text :
https://doi.org/10.1049/el.2010.1278