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Neuristor propagation in low impedance line.
- Source :
-
International Journal of Electronics . Aug70, Vol. 29 Issue 2, p101. 37p. 15 Black and White Photographs, 7 Diagrams, 16 Graphs. - Publication Year :
- 1970
-
Abstract
- This paper describes the character of neuristor operation composed of a lumped parameter delay line with a negative resistance element parallel to the capacitance, as a function of the precise character of the negative resistance element. This model allows a neuristor pulse transmission in cases with very low characteristic impedance Z<SUB0>= (L/C). The experiments cover a Z<SUB0> value down to 11 <Ohgr>. A lower characteristic impedance is possible. The model is analyzed applying Lienard's graphical method and linear approximations. As a result the criteria for characteristic parameters of negative resistance elements to operate as a neuristor are obtained. Based on the results, a neuristor with low inductance, small power, and high-speed operation can be designed. This circuit is convenient for neuristor logic, because, compared with the peculiar pulse width, it has a long delay time per section. The paper also describes neuristor logic without, an R-type junction, using only the threshold property of the neuristor. A conventional Crane's R-junction is also presented. For this neuristor model a destructive collision phenomenon exists independent of the refractory period phenomena. The mechanisms of these phenomena are clarified. [ABSTRACT FROM AUTHOR]
- Subjects :
- *ELECTRIC impedance
*ELECTRIC resistance
*ELECTRIC capacity
Subjects
Details
- Language :
- English
- ISSN :
- 00207217
- Volume :
- 29
- Issue :
- 2
- Database :
- Academic Search Index
- Journal :
- International Journal of Electronics
- Publication Type :
- Academic Journal
- Accession number :
- 5260458