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P+/n junction leakage in thin selectively grown Ge-in-STI substrates

Authors :
Eneman, G.
Yang, R.
Wang, G.
De Jaeger, B.
Loo, R.
Claeys, C.
Caymax, M.
Meuris, M.
Heyns, M.M.
Simoen, E.
Source :
Thin Solid Films. Feb2010, Vol. 518 Issue 9, p2489-2492. 4p.
Publication Year :
2010

Abstract

Abstract: This work analyses ultra-shallow pFET junctions in 330nm-thin germanium virtual substrates, selectively grown in the active regions of Shallow Trench Isolation (STI) patterned silicon wafers. The area leakage is 5–10 times higher than similar junctions in thick Ge virtual substrates if a Post-Growth (PG) anneal is done to reduce the density of threading dislocations. On the other hand, there is a factor of 10 lower perimeter leakage, thanks to the presence of the STI. The dominant generation mechanism is Trap-Assisted Tunneling up to 1V reverse bias, both for the area- and perimeter-generated leakage, as has been confirmed by measurements at elevated temperatures. Negligible frequency dispersion is found for reverse biases below 3V. However, at high reverse bias, significant frequency dispersion of the junction capacitance is found, which can be attributed to a higher defect density near the Ge/Si interface. [Copyright &y& Elsevier]

Details

Language :
English
ISSN :
00406090
Volume :
518
Issue :
9
Database :
Academic Search Index
Journal :
Thin Solid Films
Publication Type :
Academic Journal
Accession number :
48118664
Full Text :
https://doi.org/10.1016/j.tsf.2009.09.123