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Process Variation-Aware Adaptive Cache Architecture and Management.

Authors :
Mutyam, Madhu
Feng Wang
Krishnan, Ramakrishnan
Narayanan, Vijaykrishnan
Kandemir, Mahmut
Yuan Xie
Irwin, Mary Jane
Source :
IEEE Transactions on Computers. Jul2009, Vol. 58 Issue 7, p865-877. 13p. 6 Diagrams, 2 Charts, 12 Graphs.
Publication Year :
2009

Abstract

Fabricating circuits that employ ever-smaller transistors leads to dramatic variations in critical process parameters. This in turn results in large variations in execution/access latencies of different hardware components, This situation is even more severe for memory components due to minimum-sized transistors used in their design. Current design methodologies that are tuned for the worst case scenarios are becoming increasingly pessimistic from the performance angle, and thus, may not be a viable option at all for future designs. This paper makes two contributions targeting on-chip data caches. First, it presents an adaptive cache management policy based on nonuniform cache access, Second, it proposes a latency compensation approach that employs several circuit-level techniques to change the access latency of select cache lines based on the criticalities of the load instructions that access them. Our experiments reveal that both these techniques can recover significant amount of the lost performance due to worst case designs. [ABSTRACT FROM AUTHOR]

Details

Language :
English
ISSN :
00189340
Volume :
58
Issue :
7
Database :
Academic Search Index
Journal :
IEEE Transactions on Computers
Publication Type :
Academic Journal
Accession number :
43096152
Full Text :
https://doi.org/10.1109/TC.2009.30