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Low-power, high-gain and low-noise CMOS distributed amplifier for UWB systems.
- Source :
-
Electronics Letters (Institution of Engineering & Technology) . 6/4/2009, Vol. 45 Issue 12, p634-636. 3p. 1 Diagram, 1 Chart, 1 Graph. - Publication Year :
- 2009
-
Abstract
- A 3–10 GHz CMOS distributed amplifier (DA) with flat and low noise figure (NF) and flat and high power gain (S21) is demonstrated. A flat and low NF was achieved by adopting an RL terminating network for the gate transmission line, and a slightly under-damped Q-factor for the second-order NF frequency response. Besides, an flat and high S21 was achieved by using the proposed cascade gain cell, which constitutes a cascode-stage with a low-Q RLC load and an inductive-peaking common-source stage. In the high-gain mode, the DA consumed 37.8 mW and achieved a flat and high S21 of 20.47±0.72 dB with an average NF of 3.29 dB over the 3–10 GHz band of interest, one of the best reported NF performances for a CMOS UWB DA or low-noise amplifier. In the low-gain mode, the DA achieved S21 of 11.03±0.98 dB and an average NF of 4.25 dB with a power dissipation (PD) of 6.86 mW, the lowest PD ever reported for a CMOS UWB DA or LNA with an average S21 of greater than 10 dB. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 00135194
- Volume :
- 45
- Issue :
- 12
- Database :
- Academic Search Index
- Journal :
- Electronics Letters (Institution of Engineering & Technology)
- Publication Type :
- Academic Journal
- Accession number :
- 40837840
- Full Text :
- https://doi.org/10.1049/el.2009.0354