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Implementation and evaluation of a microthread architecture
- Source :
-
Journal of Systems Architecture . Mar2009, Vol. 55 Issue 3, p149-161. 13p. - Publication Year :
- 2009
-
Abstract
- Abstract: Future many-core processor systems require scalable solutions that conventional architectures currently do not provide. This paper presents a novel architecture that demonstrates the required scalability. It is based on a model of computation developed in the AETHER project to provide a safe and composable approach to concurrent programming. The model supports a dynamic approach to concurrency that enables self-adaptivity in any environment so the model is quite general. It is implemented here in the instruction set of a dynamically scheduled RISC processor and many such processors form a microgrid. Binary compatibility over arbitrary clusters of such processors and an inherent scalability in both area and performance with concurrency exploited make this a very promising development for the era of many-core chips. This paper introduces the model, the processor and chip architecture and its emulation on a range of computational kernels. It also estimates the area of the structures required to support this model in silicon. [Copyright &y& Elsevier]
- Subjects :
- *ARCHITECTURE
*SYSTEMS design
*ELECTRONIC data processing
*COMPUTER science
Subjects
Details
- Language :
- English
- ISSN :
- 13837621
- Volume :
- 55
- Issue :
- 3
- Database :
- Academic Search Index
- Journal :
- Journal of Systems Architecture
- Publication Type :
- Academic Journal
- Accession number :
- 36973270
- Full Text :
- https://doi.org/10.1016/j.sysarc.2008.07.001