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Implementation of Modeling and Simulation in Semiconductor Wafer Fabrication with Time....
- Source :
-
IEEE Transactions on Semiconductor Manufacturing . Aug2000, Vol. 13 Issue 3, p273. 5p. 2 Diagrams, 8 Graphs. - Publication Year :
- 2000
-
Abstract
- Examines the impact of time constraints on the machine capacity in semiconductor wafer fabrication in the United States. Difficulty of achieving cycle time targets; Analysis of time constraints using discrete event simulation; Installation of time windows between special wet etch and furnace operations to prevent native oxidation on the wafer surface.
- Subjects :
- *SEMICONDUCTOR wafers
*MACHINE theory
*DISCRETE-time systems
Subjects
Details
- Language :
- English
- ISSN :
- 08946507
- Volume :
- 13
- Issue :
- 3
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Semiconductor Manufacturing
- Publication Type :
- Academic Journal
- Accession number :
- 3542421
- Full Text :
- https://doi.org/10.1109/66.857935