Solving the gate ACLV and ADLV challenges with printing assist features.

The article discusses ways to enhance across-chip and across-device linewidth variation (ACLV and ADLV) against single exposure processes. It is stated that double patterning is widely employed for printing the 32nm half-pitch node using water immersion lithography. One reason is that it allows successful k1 factors below 0.25. On the other hand, double patterning also bears the likelihood of notably enhancing processes with greater k1 factors.