Circuit Noise Interference on Sampling Clock and Its Effect on A/D Conversion.

Clock jitter and its effects on signal-to-noise ratio (SNR) were widely investigated in the published literatures. However, most of the issues mainly focused on white-Gaussian-noise-only clock jitter, based on the scenario (assumption) of ideal interference-free clock circuit design which never existed in reality. This paper presents a realistic analog to digital converter (ADC) performance analysis model based on better realistic circuit noise conditions, particularly investigated on the clock jitter error with the combination of Gaussian noise and circuit noise (interference). An analytical expression for the A/D conversion with such combined clock jitter error is developed. The computer simulations are presented, which showed excellent agreement with the developed expression. Also, a real experiment is carried out to bring forth a comprehensive evaluation in A/D system design. [ABSTRACT FROM AUTHOR]