Transistor- and Circuit-Design Optimization for Low-Power CMOS.

CMOS-technology scaling has moved to a power-constrained condition regardless of the application segments. Power management in advanced CMOS technology drives the need to conciliate scaling-driven fundamental material limitations with product and application evolution requirements. Flexible CMOS technologies and tighter interaction between process development and circuit/system design are needed to efficiently realize systems on a chip. This paper reviews issues associated with transistor scaling and co-optimization for power-management circuit-design schemes for active- and leakage-power control. This paper also addresses the derived trends and implications on 110 and analog-transistor scaling. [ABSTRACT FROM AUTHOR]