Design Considerations for Sub-90-nm Split-Gate Flash-Memory Cells.

This paper presents a systematic methodology to design efficient sub-90-nm split-gate Flash-memory cells and optimize the cell performance within the presently known scaling constraints. The device-simulation results show that the high-performance sub-90-nm split-gate cells can be realized by a proper optimization of the channel and asymmetric halo-doping profiles and shallow source/drain junctions. In this paper, the halo- and channel-doping profiles were optimized to achieve the target drain-programming voltage Vsp = 6.5 V for an efficient cell programming, whereas keeping the breakdown voltage BV > Vsp with tolerable leakage currents. It is shown that, using the properly optimized technology parameters, 65-nm split-gate Flash memory can be achieved with cell-read current, Ir1 ≈ 235 μA/μm, programmed cell-leakage current, Ir0 < 2.2 nA/μm at the read condition, time-to-program ≈30 μs, and time-to-erase ≈40 μs. This paper clearly demonstrates the feasibility of high-performance 65-nm split-gate Flash-memory cells. [ABSTRACT FROM AUTHOR]