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A Simulation Study of the Switching Times of 22- and 17-nm Gate-Length SOI nFETs on High Mobility Substrates and Si.

A Simulation Study of the Switching Times of 22- and 17-nm Gate-Length SOI nFETs on High Mobility Substrates and Si.

Authors :
Laux, Steven E.
Source :
IEEE Transactions on Electron Devices. Sep2007, Vol. 54 Issue 9, p2304-2320. 17p. 2 Black and White Photographs, 1 Chart, 1 Graph.
Publication Year :
2007

Abstract

The switching times of ultrathin body semiconductor-on-insulator n-channel field-effect transistors with 22- and 17-nm gate lengths are simulated, and the results obtained for four high mobility substrates (Ge, GaAs, InP, and In0.53Ga0.47As) are compared to Si. Both intrinsic and extrinsic device structures are simulated, and a detailed accounting of device behavior is given. The most important assumptions in this paper are as follows: 1) All devices meet a 270-nA/μm leakage specification at VDD = 1 V, including band-to-band tunneling, and 2) an ideal gate insulator is posited which obtains negligible gate leakage and surface scat- tering for all semiconductors. From the extrinsic device results, it is found that, at a 22-nm gate length, switching times for the semiconductors considered vary, at most, by a factor of two, while at 17 nm, they vary by, at most, a factor of 2.5; in both cases, In0.53Ga0.47As provides the best switching time, and Si, the worst switching time. [ABSTRACT FROM AUTHOR]

Details

Language :
English
ISSN :
00189383
Volume :
54
Issue :
9
Database :
Academic Search Index
Journal :
IEEE Transactions on Electron Devices
Publication Type :
Academic Journal
Accession number :
26695622
Full Text :
https://doi.org/10.1109/TED.2007.902864