Cite
PROCESSOR DESIGN IN 3D DIE-STACKING TECHNOLOGIES.
MLA
Loh, Gabriel H., et al. “Processor Design in 3D Die-Stacking Technologies.” IEEE Micro, vol. 27, no. 3, May 2007, pp. 31–48. EBSCOhost, https://doi.org/10.1109/MM.2007.59.
APA
Loh, G. H., Yuan Xie, & Black, B. (2007). Processor Design in 3D Die-Stacking Technologies. IEEE Micro, 27(3), 31–48. https://doi.org/10.1109/MM.2007.59
Chicago
Loh, Gabriel H., Yuan Xie, and Bryan Black. 2007. “Processor Design in 3D Die-Stacking Technologies.” IEEE Micro 27 (3): 31–48. doi:10.1109/MM.2007.59.