ASYMMETRIC TUNNELING SOURCE MOSFETS:: A NOVEL DEVICE SOLUTION FOR SUB-100NM CMOS TECHNOLOGY.

MLA

Girish, N. V., et al. “Asymmetric Tunneling Source Mosfets:: A Novel Device Solution for Sub-100Nm Cmos Technology.” International Journal of High Speed Electronics & Systems, vol. 16, no. 1, Mar. 2006, pp. 95–102. EBSCOhost, https://doi.org/10.1142/S0129156406003552.

APA

Girish, N. V., Jhaveri, R., & Woo, J. C. S. (2006). Asymmetric Tunneling Source Mosfets:: A Novel Device Solution for Sub-100Nm Cmos Technology. International Journal of High Speed Electronics & Systems, 16(1), 95–102. https://doi.org/10.1142/S0129156406003552

Chicago

Girish, N. V., Ritesh Jhaveri, and J. C. S. Woo. 2006. “Asymmetric Tunneling Source Mosfets:: A Novel Device Solution for Sub-100Nm Cmos Technology.” International Journal of High Speed Electronics & Systems 16 (1): 95–102. doi:10.1142/S0129156406003552.