New Methodology for Combined Simulation of Delta-I Noise Interaction With Interconnect Noise for Wide, On-Chip Data-Buses Using Lossy Transmission-Line Power-Blocks.

A new technique is described for reducing computational complexity and improving accuracy of combined power distribution and interconnect noise prediction for wide, on-chip data-buses. The methodology uses lossy transmission-line power-blocks with frequency-dependent properties needed for the multigigahertz clock frequencies. The interaction between delta-I noise, common-mode noise, and crosstalk and their effect on timing is illustrated with simulations using representative driver and receiver circuits and on-chip interconnections. [ABSTRACT FROM AUTHOR]