Scalable on-chip multiplexing of silicon single and double quantum dots.

Owing to the maturity of complementary metal oxide semiconductor (CMOS) microelectronics, qubits realized with spins in silicon quantum dots (QDs) are considered among the most promising technologies for building scalable quantum computers. For this goal, ultra-low-power on-chip cryogenic CMOS (cryo-CMOS) electronics for control, read-out, and interfacing of the qubits is an important milestone. We report on-chip interfacing of tunable electron and hole QDs by a 64-channel cryo-CMOS multiplexer with less-than-detectable static power dissipation. We analyze charge noise and measure state-of-the-art addition energies and gate lever arm parameters in the QDs. We correlate low noise in QDs and sharp turn-on characteristics in cryogenic transistors, both fabricated with the same gate stack. Finally, we demonstrate that our hybrid quantum-CMOS technology provides a route to scalable interfacing of a large number of QD devices, enabling, for example, variability analysis and QD qubit geometry optimization, which are prerequisites for building large-scale silicon-based quantum computers. The integration of quantum dot spin qubits and classical cryogenic microelectronics is important for scaling up silicon-based quantum computers. The authors show that their silicon technology tailored for low-power electronics and low-noise quantum dots enables the integration of classical multiplexers and quantum dot spin qubit devices on the same chip. [ABSTRACT FROM AUTHOR]