A low-power keyword spotting system with SRAM buffer and computing-in-memor.

This paper proposes a low-power keyword spotting (KWS) system to overcome the problem of high-power consumption caused by deploying KWS algorithms on edge computing hardware, which can significantly impact the endurance of mobile devices. The proposed KWS system is based on computing-in-memory (CIM) technology and software-hardware co-design. In terms of algorithm, a ternary quantized MFCC-CNN joint algorithm based on the standard MFCC algorithm topology is proposed. All the general matrix multiplication (GEMM) in MFCC is mapped to the neural network accelerator. At the circuit level, the proposed system uses a computing-in-memory (CIM) core based on SRAM to overcome the power and memory walls in traditional von Neumann architecture accelerators. Additionally, a SRAM buffer circuit based on a look-up table is proposed to replace the register delay chain, which multiplexes the memory array in the CIM core. Both the SRAM-based CIM core and buffer are implemented using custom circuit units. At the system level, a low-power KWS system is proposed utilizing the two customized circuits discussed above. The system is implemented using ASIC and customized circuit design methods and synthesized using a 28 nm process library. The proposed system achieves a processing delay of 64 ms on 10 classification tasks, with a total power consumption of 645.28 μW. The dynamic power consumption of the MFCC pipeline accounts for 5.9% of the total dynamic power consumption, and the total power consumption accounts for only 1.3% of the system's power consumption. [ABSTRACT FROM AUTHOR]