Formal timing analysis of gate-level digital circuits using model checking.

MLA

Ain, Qurat-ul, and Osman Hasan. “Formal Timing Analysis of Gate-Level Digital Circuits Using Model Checking.” Microprocessors & Microsystems, vol. 109, Sept. 2024, p. N.PAG. EBSCOhost, https://doi.org/10.1016/j.micpro.2024.105083.

APA

Ain, Q., & Hasan, O. (2024). Formal timing analysis of gate-level digital circuits using model checking. Microprocessors & Microsystems, 109, N.PAG. https://doi.org/10.1016/j.micpro.2024.105083

Chicago

Ain, Qurat-ul, and Osman Hasan. 2024. “Formal Timing Analysis of Gate-Level Digital Circuits Using Model Checking.” Microprocessors & Microsystems 109 (September): N.PAG. doi:10.1016/j.micpro.2024.105083.