Performance improvement of planar silicon nanowire field effect transistors via catalyst atom doping control.

Catalytic growth of silicon nanowires (SiNWs), mediated by metallic droplet, provide ideal quasi-1D channels to construct high performance field effect transistor (FET). However, the incorporation of catalytic metal atoms into SiNWs channels has significant impact on the FET characteristics, and thus needs to be better understood and controlled to fulfil its potential for high performance electronics. In this work, we focus on the effect of the incorporation of indium (In) catalytic atoms into planar SiNWs, grown via an in-plane solid-liquid-solid (IPSLS) mechanism, on the FET device performance. It is found that the initial high concentration of p-type In dopants in the as-grown SiNWs led to an equivalent boron (B) doping of 5×1018 cm−3. However, a simple step-wise annealing in oxygen at different temperatures, varied from 620 °C to 920 °C, can help to out-diffuse the dissolved In atoms into the surface SiO 2 layer, and reduce the In concentrations down to <5×1017 cm−3, as verified by atom-probe tomography (APT) and four-point-probe measurements. This effective dopant control enables a remarkable device performance improvement of the Schottky barrier FETs, built upon an orderly array of parallel SiNWs of approximately 25 nm in diameter, where the current ratio (I on /I off) has been substantially boosted from 105 to 108, while the subthreshold swing (SS) reduced from 400 mV/dec down to ∼100 mV/dec, with a hole carrier mobility increased from 10 to ∼75 cm2 V−1 s−1 as extracted according to a finite element analysis. These results pave the way for the employment of the catalytic IPSLS SiNWs to serve as high quality 1D channels for high-performance SiNWs-based electronics and sensors. • High-density terrace-confined parallel ultrathin SiNWs arrays (D SiNW ∼25 nm) can be achieved by in-plane solid-liquid-solid growth mechanism at low growth temperature. • Catalytic In dopants concentrations in the SiNWs can be effectively reduced and controlled with oxidation-diffusion-cleaning strategy at elevated temperature. • High-performance SiNW-FETs built on the post-growth annealed ideal SiNWs channels can achieve a high I on/off ratio >108, subthreshold swing∼100 mV/dec, and d hole mobility∼75 cm2/V·s. [ABSTRACT FROM AUTHOR]