A New Approximate (8; 2) Compressor for Image Processing Applications.

Approximate computing is one of the methods to improve performance in various error-resilient applications such as image and video processing. Multipliers are part of their computing unit that often requires many resources. In this paper, an approximate (8; 2) compressor is designed and compared with other available approximate compressors for quality, power consumption, delay and area in the circuit. The proposed approximate compressor is used in $ 8 \times 8 $ 8 × 8 and $ 16 \times 16 $ 16 × 16 multipliers. To show the quality of the proposed compressor, the proposed approximate multiplier of $ 8 \times 8 $ 8 × 8 used to multiply two images in MATLAB tools, then qualitative parameters of SSIM and PSNR were measured and acceptable results were obtained. Also, the MED and NED accuracy parameters indicate the acceptable error rate in the output of the proposed $ 8 \times 8 $ 8 × 8 multiplier circuit. Finally, we synthesized the proposed approximate compressor and multiplier designs by a Synopsys Design Compiler. The proposed $ 16 \times 16 $ 16 × 16 multiplier can improve delay, area and Power Delay Products by 5%, 17%, and 8%, respectively, compared to other similar existing approximate multipliers. [ABSTRACT FROM AUTHOR]