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Efficient and lightweight in-memory computing architecture for hardware security.

Authors :
Ajmi, Hala
Zayer, Fakhreddine
Hadj Fredj, Amira
Belgacem, Hamdi
Mohammad, Baker
Werghi, Naoufel
Dias, Jorge
Source :
Journal of Parallel & Distributed Computing. Aug2024, Vol. 190, pN.PAG-N.PAG. 1p.
Publication Year :
2024

Abstract

This paper introduces an innovative solution for improving the efficiency and speed of the Advanced Encryption Standard (AES) based cryptographic algorithm. The approach leverages in-memory computing (IMC) and is versatile for application across a broad spectrum of IoT applications, including robotic autonomous vehicles and various other scenarios. To achieve this goal, memristor (MR) designs are proposed to emulate the arithmetic operations required for different phases of the AES algorithm, enabling efficient in-memory processing. The key contributions of this work include; 1) The development of a 4 bit-MR state element for implementing different arithmetic operations in an AES hardware prototype; 2) The creation of a pipeline AES design for massive parallelism and MR integration compatibility; and 3) The hardware implementation of the AES-IMC based architecture using the MR emulator. The results show that AES-IMC performs better than existing architectures in terms of higher throughput and energy efficiency. Compared to conventional AES hardware, AES-IMC achieves a 30% power enhancement with comparable throughput. Additionally, when compared to state-of-the-art AES-based NVM engines, AES-IMC demonstrates comparable power dissipation and a 62% increase in throughput. The IMC architecture enables cost-effective real-time deployment of AES, leading to high-performance computing. By leveraging the power of in-memory computing, this system is able to provide improved computational efficiency and faster processing speeds, making it a promising solution for a wide range of applications in the field of autonomous driving and robotics. The potential benefits of this system include improved safety and security of unmanned devices, as well as enhanced performance and cost-effectiveness in a variety of computing environments. • Innovative use of IMC and MR for AES processing. • Pipeline AES design with 64-bit units for high parallelism. • Superior throughput and energy efficiency of AES-IMC. • Cost-effective real-time deployment for unmanned devices. • Improved safety and security with AES-IMC. [ABSTRACT FROM AUTHOR]

Details

Language :
English
ISSN :
07437315
Volume :
190
Database :
Academic Search Index
Journal :
Journal of Parallel & Distributed Computing
Publication Type :
Academic Journal
Accession number :
177032372
Full Text :
https://doi.org/10.1016/j.jpdc.2024.104898