Linear programming-based multi-objective floorplanning optimization for system-on-chip.

In the area of very large-scale integrated circuit design, optimizing floorplans for area, wirelength, and temperature poses a daunting challenge. This study introduces an innovative floorplanning approach that amalgamates the rectangular packing method with linear programming techniques to ensure optimal module placement in the core area. Leveraging linear programming, this model optimizes three vital layout floorplanning objectives namely area, wirelength, and temperature through an analytical cost function termed linear programming-based multi-objective floorplanning. To enhance the optimization process, adaptive weights are employed for each constraint, effectively preventing congestion and hotspots. To validate the efficacy of the proposed automated floorplanning approach, extensive simulations and synthesis were conducted on benchmark circuits sourced from the Microelectronic Centre of North Carolina and Gigascale Systems Research Center. Comparative analysis with existing solutions demonstrates a significant improvement of 13%, 12% in area, and wirelength, respectively. These outcomes underscore the superior performance and practicality of the proposed floorplanning methodology, showcasing its potential for widespread application in chip design. [ABSTRACT FROM AUTHOR]