On the Layout-Oriented Investigation of Power Attack Hardness of Spintronic-Based Logic Circuits.

High leakage power consumption has become one of the main concerns of data security protection with CMOS device scaling. Spintronic technology is one of the efficient solutions to control circuit leakage power consumption by benefiting from its non-volatility property. Spintronic devices such as magnetic tunnel junctions (MTJs) are also compatible with CMOS transistors and suitable for designing hybrid MTJ/CMOS circuits. Hybrid MTJ/CMOS circuits can be used in many applications, such as logic-in-memory (LiM) and high-security structures. These circuits demonstrate enhanced data security compared to CMOS-based circuits by leveraging their non-volatile feature, making information leakage and data access more challenging. However, these circuits are not completely immune to attacks, and information can be revealed by potent power analysis attacks such as differential power analysis (DPA) and correlation power analysis (CPA). This paper investigates the resistance to side-channel attacks, especially DPA and CPA, for the magnetoresistive RAM (MRAM) and hybrid MTJ/CMOS AND, OR, XOR gates, hybrid MTJ/CMOS full-adder, and multiplexer circuits. Comprehensive post-layout simulation results using 40 nm TSMC CMOS technology, Monte-Carlo results, and values of normalized energy deviation (NED), normalized standard deviation (NSD)), and normalized power deviation (NPD) of PCSA-based MRAM indicate that the power consumption pattern remains constant in circuits with symmetrical structures in the reading phase even in the presence of inevitable process variation, so these circuits are resilient to power attacks and are competent for use in high-security applications such as hardware implementation of encryption algorithms. [ABSTRACT FROM AUTHOR]