RNS based FIR filter design with memory less distributed arithmetic filtering for high speed and low power applications.

This paper describes a high-performance RNS (Residue Number System) based FIR filter design using distinct memory-based and memory-less Distributed-Arithmetic (DA) approaches. The suggested RNS FIR filter implementation with core optimized RNS has the advantage of reducing hardware complexity overhead while increasing operating performance. Look-Up-Table (LUT)-less design has multiplexers and adders in place of DA's LUTs, resulting in reduced size and power consumption. LUT-less DA II will work faster than any other circuits with reduced Logic Elements (LEs) and consumes less power. In this paper, the metrics like delay, area, power, Area-Delay-Product (ADP), Power-Delay-Product (PDP), and maximum frequency were calculated using Verilog HDL. Finally, the metrics are compared for 4-tap 8-tap, and 16-tap. The logical elements were decreased by 17.09%, the frequency was increased by 3.18%, and the power dissipation was marginally decreased when compared to the modified DA FIR design with the suggested Memory less DA II. [ABSTRACT FROM AUTHOR]