Back to Search
Start Over
SPCTRE: sparsity-constrained fully-digital reservoir computing architecture on FPGA.
- Source :
-
International Journal of Parallel, Emergent & Distributed Systems . Apr2024, Vol. 39 Issue 2, p197-213. 17p. - Publication Year :
- 2024
-
Abstract
- This paper proposes an unconventional architecture and algorithm for implementing reservoir computing on FPGA. An architecture-oriented algorithm with improved throughput and architecture designed to reduce memory and hardware resource requirements are presented. The proposed architecture exhibits good performance in terms of benchmarks for reservoir computing. A prediction accelerator for reservoir computing that operates on 55.45 mW at 450 K fps with <3000 LEs is realized by implementing the architecture on FPGA. The proposed approach presents a novel FPGA implementation of reservoir computing focussing on both algorithms and architecture that may serve as a basis for applications of AI at network edge. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 17445760
- Volume :
- 39
- Issue :
- 2
- Database :
- Academic Search Index
- Journal :
- International Journal of Parallel, Emergent & Distributed Systems
- Publication Type :
- Academic Journal
- Accession number :
- 175749755
- Full Text :
- https://doi.org/10.1080/17445760.2024.2310576