FPGA design of arithmetic optimised APT-VDF using reusable Vedic multiplier with simplified combinational logics for medical signal denoising.

All-pass transformation (APT)-based variable digital filters (VDFs) can be used in different biomedical signal-processing applications, particularly in electrocardiograph denoising. In this paper, arithmetic optimised APT-VDF is proposed by modifying the hardware structure of APT-VDF based on arithmetic perception to enhance the performance in terms of area, speed and power consumption. The core blocks of the suggested Arithmetic Optimised APT-VDF (AOAPT-VDF)are adders and multipliers. This paper introduces a new reusable Vedic multiplier with redundant detection unit to identify redundant computations while generating the partial products. Also, a new Carry select adder (CSLA) with simplified combinational logics is proposed to improve the performance of the CSLA by simplifying the partial sum and carry generation logics without requiring Ripple Carry Adders. The proposed Reusable Vedic Multiplier with Redundant Detection Logic (RVM-RDL) also reuses the same vertical and cross-product generation units repetitively to reduce the area while increasing the bit length. The effectiveness of the suggested AOAPT is analysed utilising the MIT-BIH Arrhythmia Database. The proposed AOAPT-VDF consumes only 0.21 $$W$$ W power and achieves a 235.50 MHz operating frequency. [ABSTRACT FROM AUTHOR]