Design and implementation of 8 - bit multiplier using carry adder by comparing with carry look ahead.

The main objective of this research is to design a novel wallace multiplier using CSA (Carry Select Adder) to obtain the less propagation delay time (in ns) when compared to wallace multiplier using CLA (Carry Look Ahead Adder). With a sample size of ten, the proposed system uses CSA as group 1 to test a novel wallace multiplier, while the existing system uses CLA as group 2 to test a system with pre-test power of 80%. The wallace multiplier was designed in the open source software Model Sim. A waveform is displayed at output with propagation delay time and some binary values after designing the multiplier in the Model Sim software. The novel wallace multiplier using CSA takes very less propagation delay of 700 ns whereas the wallace multiplier using CLA takes the 800 ns of propagation delay which is very high. The significance value obtained was 0.0121 (p<0.05). From the simulated results novel wallace multiplier using CSA shows less propagation delay, less power consumption and less size when compared to wallace multiplier using CLA. [ABSTRACT FROM AUTHOR]