SystemC-based Co-Simulation/Analysis for System-Level Hardware/Software Co-Design.

• Electronic system-level HW/SW co-design of heterogeneous parallel embedded systems. • SystemC-based electronic system-level functional and timing HW/SW co-simulation. • System-level multi model of computation co-analysis (communication and concurrency). • System-level multi model of computation co-estimation (load and bandwidth). • Support to automatic electronic system-level design space exploration. Heterogeneous parallel devices are becoming increasingly common in the embedded systems field. This is primarily due to their ability to improve timing performance, while simultaneously reducing costs and energy. In this context, this study addresses the role of a hardware/software (HW/SW) co-simulation and analysis tool for embedded systems designed on heterogeneous parallel architectures. In particular, it presents an extended System C-based tool for functional and timing HW/SW co-simulation/analysis within a reference Electronic System-Level HW/SW co-design flow. The description of the main features of the tool, and the main design and integration issues represent the core of the paper. Furthermore, the paper presents two case studies that demonstrate the enhanced effectiveness and efficiency of the extended tool. This is achieved through reduced simulation. Thanks to all this, the paper contributes to fully motivate the industrial and research communities to adopt and further investigate system-level approaches. [Display omitted] [ABSTRACT FROM AUTHOR]