Cite
Single and double-adjacent error correcting code (SDECC) with lower design overheads and mis-correction rate for SRAMs.
MLA
Maity, Raj Kumar, et al. “Single and Double-Adjacent Error Correcting Code (SDECC) with Lower Design Overheads and Mis-Correction Rate for SRAMs.” Microsystem Technologies, vol. 29, no. 6, June 2023, pp. 823–34. EBSCOhost, https://doi.org/10.1007/s00542-023-05464-3.
APA
Maity, R. K., Samanta, J., & Bhaumik, J. (2023). Single and double-adjacent error correcting code (SDECC) with lower design overheads and mis-correction rate for SRAMs. Microsystem Technologies, 29(6), 823–834. https://doi.org/10.1007/s00542-023-05464-3
Chicago
Maity, Raj Kumar, Jagannath Samanta, and Jaydeb Bhaumik. 2023. “Single and Double-Adjacent Error Correcting Code (SDECC) with Lower Design Overheads and Mis-Correction Rate for SRAMs.” Microsystem Technologies 29 (6): 823–34. doi:10.1007/s00542-023-05464-3.