Low power VLSI architecture for hamming encoder and decoder using verilog HDL.

The field of communication has produced many applications in the digital world. The input message or data is encoded by the transmitter in most communication sectors and transmitted via the communication channel. Data is retrieved from the receiver and original data is successfully recovered after the decoding of the received data. In several popular applications, including optical storage devices, random access memory, wireless communication system. It is possible to introduce noise to a communication channel. Noise affects the input data and data could get corrupted during the transmission. In existing method, at a rate of 1⁄2 convolution coding with a restriction length of K=2, this method has a low-speed encoder/decoder (11, 7, 1). It works at moderate power consumption and high delay are seen. This Proposed method has a low power and High speed encoder/decoder at a rate of 1⁄2 convolution coding with a restriction length of K=3. A high speed and low delay are presented (12,4,1). It is important that the receiver has some features that are able to locate the error at the end of the receiver. Hamming error detection and correction code are used. Low power and high-speed encoder/decoder is constructed using separate FPGA boards and using all logics together in one IC at the same time. The Proposed circuit is developed using Verilog HDL and the functions have been validated on the basis of the ISE simulator obtained using Xilinx 14.7 tool. [ABSTRACT FROM AUTHOR]