Cite
Low Latency TOE with Double-Queue Structure for 10Gbps Ethernet on FPGA.
MLA
Yang, Dan, et al. “Low Latency TOE with Double-Queue Structure for 10Gbps Ethernet on FPGA.” Sensors (14248220), vol. 23, no. 10, May 2023, p. 4690. EBSCOhost, https://doi.org/10.3390/s23104690.
APA
Yang, D., Xu, X., Chen, T., Chen, Y., & Zhang, J. (2023). Low Latency TOE with Double-Queue Structure for 10Gbps Ethernet on FPGA. Sensors (14248220), 23(10), 4690. https://doi.org/10.3390/s23104690
Chicago
Yang, Dan, Xuhan Xu, Tianyang Chen, Yanhao Chen, and Junjie Zhang. 2023. “Low Latency TOE with Double-Queue Structure for 10Gbps Ethernet on FPGA.” Sensors (14248220) 23 (10): 4690. doi:10.3390/s23104690.