Coprocesador de multiplicación en Fp² para la aceleración de emparejamientos bilineales en SoC-FPGA.

This paper focuses on the implementation of a hardware coprocessor intended to speed up multiplications over the Fp² finite field extension in the context of bilinear pairings. Being aware of the high degree of parallelism present at different levels of pairings computation, especially in the case of Fp² multiplications, we propose a hardware architecture based on internal and external pipeline structures allowing both, accelerate a single multiplication and perform several multiplications in parallel. This enables the development of a hybrid hardware/software solution on a SoC-FPGA for computing bilinear pairings that improves the performance of equivalent state-of-the-art implementations up to a 22.5%. [ABSTRACT FROM AUTHOR]