Cite
Design of Power, Area and Delay Optimized Direct Digital Synthesizer Using Modified 32-Bit Square Root Carry Select Adder.
MLA
Ganna, Raju, et al. “Design of Power, Area and Delay Optimized Direct Digital Synthesizer Using Modified 32-Bit Square Root Carry Select Adder.” Journal of Circuits, Systems & Computers, vol. 31, no. 17, Nov. 2022, pp. 1–23. EBSCOhost, https://doi.org/10.1142/S0218126622502929.
APA
Ganna, R., Saxena, S., & Patel, G. S. (2022). Design of Power, Area and Delay Optimized Direct Digital Synthesizer Using Modified 32-Bit Square Root Carry Select Adder. Journal of Circuits, Systems & Computers, 31(17), 1–23. https://doi.org/10.1142/S0218126622502929
Chicago
Ganna, Raju, Shanky Saxena, and Govind Singh Patel. 2022. “Design of Power, Area and Delay Optimized Direct Digital Synthesizer Using Modified 32-Bit Square Root Carry Select Adder.” Journal of Circuits, Systems & Computers 31 (17): 1–23. doi:10.1142/S0218126622502929.