Efficient hardware implementations of lightweight Simeck Cipher for resource-constrained applications.

Due to the vigorous and ever-evolving demands of the IoT field, resource-constrained devices are being deployed in such areas and several new challenges like sequestration and surveillance, have come into the picture. Multiple lightweight designs have been recommended to overcome the security issues for resource-constrained devices. In applications requiring data to be transmitted fast between various devices, loop unrolling and subsequent pipelining architectures are extremely efficient. In this paper, several efficient hardware implementations of Simeck cipher such as loop unrolling architecture and outer round pipelining technique have been proposed in order to achieve high throughput. This paper has also proposed a bit serialized architecture of the Simeck cipher that reduces the area footprint and used in less resource applications. Our Simeck Serial architecture is 29.5 times more efficient than LiCi cipher and occupies only 7% of the area occupied by LiCi cipher. Similarly, our proposed serial architecture occupies only 13% and 25% of total slices occupied by X 192 and XTEA respectively while still performs 184% and 161% more efficiently. All three architectures are evaluated and compared on the basis of throughput, area utilization, and power consumption for their implementations in different FPGA platforms. • In unroll loop architecture of Simeck cipher, all rounds are unrolled which ultimately vastly reduces the latency while providing an optimum trade-off between area footprint and performance. This makes the design fit for applications demanding less latency. • The proposed outer round pipelining architecture is in turn derived from the full loop unrolling architecture where the loop unrolling greatly simplifies the key scheduling and the round function of the Simeck cipher. With the installation of registers in between each round, throughput is significantly improved and the area footprint is also reduced making design relevant for low resource and high-speed applications. • The proposed serial architecture for Simeck cipher utilizes only 17 slices making it extremely area efficient. [ABSTRACT FROM AUTHOR]