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Machine learning based fast and accurate High Level Synthesis design space exploration: From graph to synthesis.
- Source :
-
Integration: The VLSI Journal . Jan2023, Vol. 88, p116-124. 9p. - Publication Year :
- 2023
-
Abstract
- In this paper, we present a machine learning based High-Level Synthesis (HLS) design space explorer (DSE) that significantly reduces the exploration runtime while leading to very accurate results. In order to do so, we leverage the power of low level virtual machine (LLVM) to generate the features used in the machine learning (ML) model. The proposed design space explorer uses a modified version of simulated annealing (SA) algorithm, where initially the search space is sampled to generate the predictive model. In this work we used gradient boost regression algorithm as our preferred ML model and achieve comparable results as a full DSE that performs logic synthesis for each newly generated design. • Proposed a method to converts untimed C/C++ descriptions for HLS into LLVM IR codes. • The IR code and the graphs are used to generate features for predictive models. • A gradient boost model is used to predict post route area and latency of the design. • A fast ML based design space explorer is proposed using the gradient boost model. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 01679260
- Volume :
- 88
- Database :
- Academic Search Index
- Journal :
- Integration: The VLSI Journal
- Publication Type :
- Academic Journal
- Accession number :
- 160331716
- Full Text :
- https://doi.org/10.1016/j.vlsi.2022.09.006