Cite
A High Performance Multi-Bit-Width Booth Vector Systolic Accelerator for NAS Optimized Deep Learning Neural Networks.
MLA
Huang, Mingqiang, et al. “A High Performance Multi-Bit-Width Booth Vector Systolic Accelerator for NAS Optimized Deep Learning Neural Networks.” IEEE Transactions on Circuits & Systems. Part I: Regular Papers, vol. 69, no. 9, Sept. 2022, pp. 3619–31. EBSCOhost, https://doi.org/10.1109/TCSI.2022.3178474.
APA
Huang, M., Liu, Y., Man, C., Li, K., Cheng, Q., Mao, W., & Yu, H. (2022). A High Performance Multi-Bit-Width Booth Vector Systolic Accelerator for NAS Optimized Deep Learning Neural Networks. IEEE Transactions on Circuits & Systems. Part I: Regular Papers, 69(9), 3619–3631. https://doi.org/10.1109/TCSI.2022.3178474
Chicago
Huang, Mingqiang, Yucen Liu, Changhai Man, Kai Li, Quan Cheng, Wei Mao, and Hao Yu. 2022. “A High Performance Multi-Bit-Width Booth Vector Systolic Accelerator for NAS Optimized Deep Learning Neural Networks.” IEEE Transactions on Circuits & Systems. Part I: Regular Papers 69 (9): 3619–31. doi:10.1109/TCSI.2022.3178474.