Improved thermal network modeling of die stacking DRAM and optimization.

As the dynamic random access memory (DRAM) chip tends to the larger storage capacity by die stacking, the 3D die stacking requires thermal modeling for fast temperature predicting and initial design. This work presents a theoretical model capable of fast calculating and optimizing the temperature of each die. The improved thermal network defines equivalent shape correction parameters to improve the calculation accuracy of the thermal network. The 3D die sacking derives a novel topology of improved thermal network through the division of the heat transfer path inside DRAM. The analysis demonstrates that the calculating results of improved thermal network show good consistency with the finite element method in steady and transient states thermal analysis. Beyond this, the effect of size and thermal power is discussed in the calculation accuracy. The improved thermal network is used in the optimization design of DRAM with eight-dies vertical stacking. The maximum temperature increment is reduced by 15% after optimization. • The improved thermal network of DRAM considers all heat transfer paths in the 3D die stacking. • The shape correction parameters are defined to improve the calculation accuracy of the improved thermal network. • The effects of size and thermal power on the calculation accuracy of the improved thermal network are analyzed. • The model effectiveness is verified by an optimization design of DRAM with eight-die stacking. [ABSTRACT FROM AUTHOR]