High-efficiency array-level MRAM parameters extraction with the device-in-series test structure.

The precise extraction of magnetic tunnel junction parameters at device level is important for understanding the weak point and its root cause in the stack design, which allows for future developments. The related variability is also vital for a reliable memory technology. Current test methods, however, are limited either to the material level or low efficiency. In this work, a device-in-series structure is proposed that directly monitors the statistical properties of the devices. This allows for a massively parallel measurement and, in this way, permits an accurate, high-efficiency testing with the device-to-device variability embedded intrinsically. Based on this method, we studied the temperature dependence of spin-transfer torque magnetoresistive random access memory's retention from 12 to 300 K, using a statistical domain wall switching model. The synthetic antiferromagnetic layers are more immune to the temperature change, compared with the free layer. The magnetoresistance is found to be a convex function of the temperature below 100 K, which contrasts the single-device measurements. The results show that as the temperature decreases, the domain wall shrinks and the zero-field energy barrier still increases. [ABSTRACT FROM AUTHOR]