Lightweight 8‐bit S‐box and combined S‐box/S‐box−1 for cryptographic applications.

Summary: In this paper, a lightweight 8‐bit S‐box and combined S‐box/S‐box−1 with a security level equal to the AES S‐box is presented. From the viewpoint of hardware implementation, the S‐box has better hardware and timing complexities. The structure is based on an efficient field inversion and a low‐cost affine transformation. The field multiplications over 픽24 in the inversion circuit are implemented by resource sharing to reduces logic gates. The original equations of the inversion over 픽24 are optimally rewritten. In addition, a part of the S‐box called Part1 is optimized for reducing area and delay. This part consists of two addition operations, one multiplication, field squaring, and multiplication by constant λ, which all operations are over 픽24. The subblocks of Part1 are combined to generate a unified structure. Security analysis of the proposed S‐box showed that the structure has a security level equal to the Advanced Encryption Standard (AES) S‐box. The implementation results in 180‐ and 65‐nm Complementary metal oxide semiconductor (CMOS) technologies show the proposed S‐box and combined S‐box/S‐box−1 are comparable in terms of area, delay, and area × delay than most of the famous S‐boxes. The proposed S‐box is a high‐secure and area‐efficient S‐box as a good candidate for block ciphers. [ABSTRACT FROM AUTHOR]