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A latch-up-free LVTSCR with improved overshoot characteristic for ESD protection in 40 nm CMOS process.
- Source :
-
Semiconductor Science & Technology . Jun2021, Vol. 36 Issue 6, p1-5. 5p. - Publication Year :
- 2021
-
Abstract
- In this paper, a novel robust low-voltage-triggered silicon-controlled rectifier (LVTSCR) with high holding voltage, low trigger voltage, and low overshoot voltage has been proposed for 5 V integrated circuit electrostatic discharge (ESD) protection. The new LVTSCR integrates an extra low-resistance current path by embedding an NMOS transistor into the traditional LVTSCR. This extra current path will divert part of the ESD current, thus resulting in a lower overshoot voltage as well as better quasi-static I–V characteristics in the new structure. As such, the holding voltage of the new LVTSCR has been increased by ∼23%, the quasi-static triggering characteristic has been decreased by ∼8%, and the overshoot voltage has been improved by ∼38%. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 02681242
- Volume :
- 36
- Issue :
- 6
- Database :
- Academic Search Index
- Journal :
- Semiconductor Science & Technology
- Publication Type :
- Academic Journal
- Accession number :
- 150590325
- Full Text :
- https://doi.org/10.1088/1361-6641/abf3a9