Back to Search Start Over

Efficient ASIC and FPGA implementation of cube architecture.

Authors :
Barik, Ranjan Kumar
Pradhan, Manoranjan
Source :
IET Computers & Digital Techniques (Wiley-Blackwell). Jan2017, Vol. 11 Issue 1, p43-49. 7p.
Publication Year :
2017

Abstract

This study presents a generalised architecture for cube operation based on Yavadunam sutra of Vedic mathematics. This algorithm converts the cube of a large magnitude number into smaller magnitude number and addition operation. The Vedic sutra for decimal numbers is extended to binary radix‐2 number system considering digital platforms. The cubic architecture is synthesised and simulated using Xilinx ISE 14.1 software and implemented on various Field‐programmable gate array devices for comparison purpose. The Encounter(R) RTL Compiler RC13.10 v13.10‐s006_1 of cadence tool is also used considering Application specific integrated circuit platform. The performance parameters such as delay, area and power are obtained from synthesis reports. The results show that the proposed architecture is useful for less area and high‐speed application in microprocessor environment. [ABSTRACT FROM AUTHOR]

Details

Language :
English
ISSN :
17518601
Volume :
11
Issue :
1
Database :
Academic Search Index
Journal :
IET Computers & Digital Techniques (Wiley-Blackwell)
Publication Type :
Academic Journal
Accession number :
148454831
Full Text :
https://doi.org/10.1049/iet-cdt.2016.0043