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Design optimization of nanoscale electrothermal transport in 10 nm SOI FinFET technology node.
- Source :
-
Journal of Physics D: Applied Physics . 12/2/2020, Vol. 53 Issue 49, p1-10. 10p. - Publication Year :
- 2020
-
Abstract
- A flexible framework is obtained for enhancing both the thermal and electrical performance of fin field-effect transistor (FinFET) technology. Investigation of the nanoscale heat conduction within a short-channel field-effect transistor can be regarded as an emerging challenge related to future-generation transistors. In this work, we report the electrothermal transport in a 10 nm silicon-on-insulator (SOI) FinFET based on the dual-phase-lag model and modified drift-diffusion motions. We found that electron mobility decreases along the channel due to carrier confinement under higher electric field. In addition, the surface detection temperature indicates that the self-heating process is localized between the source and drain region. As promising results, high-κ metal-oxide and lower thermal boundary resistance can optimize the nanoscale heat transport in the SOI FinFET device. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 00223727
- Volume :
- 53
- Issue :
- 49
- Database :
- Academic Search Index
- Journal :
- Journal of Physics D: Applied Physics
- Publication Type :
- Academic Journal
- Accession number :
- 146086432
- Full Text :
- https://doi.org/10.1088/1361-6463/abaf7c