Parametric study of pulsed laser deposited (PLD) WSe2 2D transistors.

A fabrication process for making large area transistors on pulsed laser deposited (PLD) WSe 2 has been developed. Large films of WSe 2 have been deposited via PLD technique on SiO 2 /Si substrate. Employing a mask-less lithography technique and using vapour XeF 2 as an etchant, transistors of lengths (17, 83, 323 and 1000 μm) and widths (14 and 850 μm) have been fabricated. Electrical characterization of the transistors show that as the channel length (L) decreases, the magnitude of the drain-source current increases. In addition, the current across the transistor has been found to increase by increasing the channel width (W). Moreover, channels with large areas have been found to deliver substantially more drain-source current compared with smaller channel areas with similar W/L. A W/L ratio of 0.85 has been found to possess the highest drain current across the transistors fabricated. From the transfer length measurement (TLM), the sheet resistance and contact resistance of the device have been measured. Field effect mobility of the transistors have been calculated. Raman spectrum shows that PLD WSe 2 possess similar quality as exfoliated WSe 2. However, Photoluminescence (PL) spectrum and TLM results suggest the lack of bandgap in our 14-layer PLD WSe 2. Unlabelled Image • Parametric study of large area 2D WSe 2 field-effect transistor (FET). • Growth of centimetre scale WSe 2 via pulsed laser deposition (PLD). • Mask-less lithography and XeF 2 etching to fabricate WSe 2 transistors. • Negative contact resistance and no photo-luminescence peaks observed in PLD WSe 2. • Transistor width to length ratio of 85% produced higher drain to source current. [ABSTRACT FROM AUTHOR]