A 1‐bit full adder using CNFET based dual chirality high speed domino logic.

MLA

Garg, Sandeep, et al. “A 1‐bit Full Adder Using CNFET Based Dual Chirality High Speed Domino Logic.” International Journal of Circuit Theory & Applications, vol. 48, no. 1, Jan. 2020, pp. 115–33. EBSCOhost, https://doi.org/10.1002/cta.2714.

APA

Garg, S., Gupta, T. K., & Pandey, A. K. (2020). A 1‐bit full adder using CNFET based dual chirality high speed domino logic. International Journal of Circuit Theory & Applications, 48(1), 115–133. https://doi.org/10.1002/cta.2714

Chicago

Garg, Sandeep, Tarun K. Gupta, and Amit K. Pandey. 2020. “A 1‐bit Full Adder Using CNFET Based Dual Chirality High Speed Domino Logic.” International Journal of Circuit Theory & Applications 48 (1): 115–33. doi:10.1002/cta.2714.