A 2.41-pJ/bit 5.4-Gb/s Dual-Loop Reference-Less CDR With Fully Digital Quarter-Rate Linear Phase Detector for Embedded DisplayPort.

MLA

Moon, Yong-Hwan, et al. “A 2.41-PJ/Bit 5.4-Gb/s Dual-Loop Reference-Less CDR With Fully Digital Quarter-Rate Linear Phase Detector for Embedded DisplayPort.” IEEE Transactions on Circuits & Systems. Part I: Regular Papers, vol. 66, no. 8, Aug. 2019, pp. 2907–20. EBSCOhost, https://doi.org/10.1109/TCSI.2019.2906877.

APA

Moon, Y.-H., Yoo, J.-W., Ryu, Y.-S., Kim, S.-H., Son, K.-S., & Kang, J.-K. (2019). A 2.41-pJ/bit 5.4-Gb/s Dual-Loop Reference-Less CDR With Fully Digital Quarter-Rate Linear Phase Detector for Embedded DisplayPort. IEEE Transactions on Circuits & Systems. Part I: Regular Papers, 66(8), 2907–2920. https://doi.org/10.1109/TCSI.2019.2906877

Chicago

Moon, Yong-Hwan, Jae-Wook Yoo, Young-Soo Ryu, Sang-Ho Kim, Kyung-Sub Son, and Jin-Ku Kang. 2019. “A 2.41-PJ/Bit 5.4-Gb/s Dual-Loop Reference-Less CDR With Fully Digital Quarter-Rate Linear Phase Detector for Embedded DisplayPort.” IEEE Transactions on Circuits & Systems. Part I: Regular Papers 66 (8): 2907–20. doi:10.1109/TCSI.2019.2906877.