A clustering/labeling analog LSI architecture for media recognition.

Clustering and labeling are basic processes in speech and image recognition. In this paper, we present the design of an analog circuit for a clustering and labeling system and the performance evaluation results based on a simulation. The number of basic computation modules becomes huge when digital LSIs are designed for parallel processing. It becomes one reason for the increase in the chip area. Therefore, we propose an architecture for a clustering/labeling circuit. It introduces the similarity circuit that utilizes the fundamental characteristics of MOS and the C matrix circuit that outputs the results of the matrix computation. We use this circuit to conduct a circuit simulation that includes statistical analysis and confirm the ability to perform feature clustering of simple speech. The proposed analog circuit has an extremely simple architecture and is expected to decrease the chip area by about 1/36 compared to an 8-bit digital design. © 2002 Wiley Periodicals, Inc. Electron Comm Jpn Pt 3, 85(10): 1–7, 2002; Published online in Wiley InterScience (<URL>www.interscience.wiley.com</URL>). DOI 10.1002/ecjc.1120 [ABSTRACT FROM AUTHOR]